Prior computer systems typically rely on standardized busses, such as the Peripheral Component Interconnect (PCI) bus, to allow computer system chipset components to communicate one with another. For example, a transaction originating at a processor and intended for a disk drive might first be delivered to a first chipset component that serves as an intermediary between the processor bus and a PCI bus. The first chipset component would then deliver the transaction over the PCI bus to a second system chipset component which would then deliver the transaction to the disk drive.
Busses such as the PCI bus also provide for communication with other computer system devices such as graphics controllers and network adapters. Because busses such as the PCI bus must interface with a variety of component types, each with varying requirements, they are not necessarily optimized for allowing communication between chipset components. Further, chipset manufacturers who rely on standardized busses such as the PCI bus must adhere to bus standards in order to ensure compatibility with other components, and are not at liberty to make substantial changes in how the chipset components communicate with each other. Another issue that faces chipset component manufacturers in designing and manufacturing chipset components is the need to conform to standardized supply and signaling voltages when relying on busses such as PCI for communication between chipset components, thereby locking the manufacturers into certain design practices and manufacturing technologies.
Prior computer systems that rely on standardized busses such as PCI for communication between chipset components also typically have no mechanism for communicating that a particular transaction is isochronous and should be handled in a manner that will ensure an adequate level of quality of service. Deterministic quality of service is particularly important for emerging applications that rely on isochronous services in the system to move fixed amount of data on a regular basis. In prior systems, the notion of isochronous transactions is contained within subsystems such as USB host controllers and IEEE 1394 host controllers, and there is no mechanism to extend this notion up to the point where transactions are serviced (the main memory subsystem).